There is an ongoing demand for semiconductor deposition systems and methods that provide high quality products while also providing high and relatively inexpensive throughput. For example, the solar power industry continues to search for improved ways to produce photovoltaic (PV) cells, and wafer silicon (Si) modules have seen decreases in manufacturing costs (or unit cost per unit of power produced (sometimes labeled $/W)), and there is need for this trend to continue for solar power to be more widely adopted. However, manufacturing cost modeling has shown that it may be difficult for both high and low efficiency wafer Si technologies to reach target cost goals (e.g., $0.50/W modules).
As one particular example of a need for new semiconductor deposition systems, III-V solar cells have world-leading efficiencies, but high production costs negate or overshadow the value delivered by higher efficiencies. The production of efficient multi-layered III-V semiconductor devices such as solar cells demands the formation of sharp interface transitions between layers of varying composition and may utilize chemical vapor deposition (CVD) processes. For example, in multi-layered PV devices, deposition of the multiple layers provided in a single junction device (e.g., back surface field, base, emitter, window) has to be able to provide transitions in composition between, for example, indium gallium phosphide (InGaP) and gallium arsenide (GaAs), with simultaneous transitions in doping type and concentration. Inaccurate placement of dopants or a graded transition in layer composition that can occur with existing deposition processes at high growth rates degrades device performance.
Presently, these types of multilayer, multi junction devices are typically deposited using metal-organic vapor phase epitaxy (MOVPE), which offers a high level of control over the epitaxial growth process. MOVPE is generally carried out under conditions in which the growth is mass transport limited. The ability to form sharp interfaces is, therefore, limited by the specific gas flow dynamics and the speed with which gases can be switched and purged from the reactor. As a result, the design of the reactor and the employed growth conditions can determine the properties of the resulting structures. There can also be interaction between the reactants and the inner surfaces of the reactor system and gas panel leading to transients in the compositional and dopant profiles. For example, hydrogen selenide (H2Se) can adsorb on stainless steel, which alters the delivery of this reactant to the growth system, and magnesium (Mg) and zinc (Zn) have demonstrated memory effects. Almost all III-V solar cells are presently grown using MOVPE because of the high material quality, interface control in multilayer devices, and the availability of highly-purified metalorganic precursors it offers, but MOVPE-based processes are very expensive. As a result, a radically different growth process is needed for III-V solar cells to obtain one-sun grid parity or to even come close to competing with Si modules.
Hydride vapor phase epitaxy (HVPE) has been demonstrated to grow a variety of junction devices at significantly higher growth rates than MOVPE and other deposition techniques such as molecular beam epitaxy (MBE). HVPE growth rates approaching or exceeding several hundred microns per hour have been demonstrated in various materials systems whereas MOVPE growth rates are much lower at 1 to 5 micrometers per hour. There is a belief that such an increase in growth rate could provide cost reductions due to a higher reactor throughput. For example, the manufacture of III-V photovoltaics could be developed into a more cost-effective approach for terrestrial energy production with an increased growth rate if high efficiencies could also be maintained in the deposition process because growth rate and not using metal organic precursor molecules lowers the cost of devices made by HVPE.
However, there are a number of challenges associated with the application of HVPE to the manufacture of semiconductor devices such as PV devices. For example, it is difficult when using HVPE to provide useful or desirable formation of both sharp interfaces (e.g., a heterojunction interface) and well-controlled doping profiles. The HVPE process is considered a near-to-equilibrium growth process allowing the growth to be modeled using equilibrium thermodynamics, and HVPE is also typically characterized by lower gas velocities and the use of a hot wall, quasi-isothermal reactor system. These reactor and growth conditions have led to difficulties in controlling interface sharpness. Device deposition can be deteriorated by the presence of transient flows, especially within the source zone where the metal chlorides (used as the active growth reactant) are formed in situ.
Various approaches have been used to mitigate these challenges including the formation of compositional and dopant transients, but none has yet proven wholly satisfactory. In some instances, individual layers are grown in separate reactors and within separate growth runs. The samples are removed from the growth zone, gas flows are switched and equilibrated, and the growth then resumed with the reintroduction of the samples to the growth zone. Generally, there are two main variations: (1) growth in a single reactor with an interruption (e.g., where either the sample is protected under H2/Group V ambient or where the sample is pulled out of the reactor completely while growth of the next layer is recalibrated); and (2) growth in a reactor that has multiple barrels with reactants of different composition (e.g., the sample is simply transferred from barrel to barrel to grow the desired layers). In some of these applications, a system has been used in which the sources are removed from the source zone after layer growth in order to halt transient growth. The use of a growth interruption may be the simplest method, but the exposure of the growth-interrupted interface to the flowing ambient while chemistry flows are reestablished leads to the accumulation of impurities at the interface and corresponding degraded electrical performance.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.